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| june 2012 ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 FAN302HLMY_f117 ? mwsaver? pwm controller for low standby power battery-charger applications FAN302HLMY_f117 pwm controller for low standby power battery- charger applications ? mwsaver? technology features ? mwsaver? technology provides industry?s best-in-class standby power - achieves <10mw below energy star?s 5-star level: <30mw - proprietary 500v high-voltage jfet startup reduces startup resistor loss - low operation current in burst mode: 350a maximum ? constant-current (cc) control without secondary- feedback circuitry ? fixed pwm frequency at 85khz with frequency hopping to reduce emi ? high-voltage startup ? low operating current: 3.5ma ? peak-current-mode control with slope compensation ? cycle-by-cycle current limiting ? v dd over-voltage protection (auto-restart) ? v s over-voltage protection (latch mode) ? v dd under-voltage lockout (uvlo) ? gate output maximum voltage clamped at 15v ? fixed over-temperature protection (latch mode) ? available in an 8-lead soic package applications ? battery chargers for cellular phones, cordless phones, pdas, digital cameras, and power tools ? replaces linear regulators and rcc smps description the FAN302HLMY_f117 advanced pwm controller significantly simplifies isolated power supply design that requires cc regulation of t he output. the output current is precisely estimated with information in the primary side of the transformer and controlled with an internal compensation circuit. this removes the output current sensing loss and eliminates all external control circuitry (cc). the green-mode function, with an extremely low operating current (200a) in burst mode, maximizes the light-load efficiency, enabling conformance to worldwide standby mode efficiency guidelines. integrated protections include two-level pulse-by-pulse current limit, over-voltage protection (ovp), brownout protection, and over-temper ature protection (otp). compared with a conventional approach using an external control circuit in the secondary side for cc regulation, the FAN302HLMY_f117 can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. figure 1. typical output v-i characteristic ordering information part number operating temperature range package packing method FAN302HLMY_f117 -40 c to +105 c 8-lead, small outline package (soic), jedec ms-012, .150-inch narrow body tape & reel i o v o maximum typical minimum
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 2 FAN302HLMY_f117? mwsaver? pwm c ontroller for low standby power battery-charger applications application diagram figure 2. typical application internal block diagram figure 3. functional block diagram ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 3 FAN302HLMY_f117? mwsaver? pwm c ontroller for low standby power battery-charger applications marking information figure 4.top mark pin configuration figure 5. pin assignments pin definitions pin # name description 1 cs current sense . this pin connects a current-sense resist or to sense the mosfet current for peak-current-mode control for output regulation. the current-sense information is also used to estimate the output current for cc regulation. 2 gate pwm signal output . this pin has an internal totem-pole output driver to drive the power mosfet. it is internally clamped at 15v. 3 vdd power supply . ic operating current and mosfet driving current are supplied through this pin. this pin is typically connected to an external v dd capacitor. 4 vs voltage sense . this pin detects the output voltage in formation and diode current discharge time based on the voltage of the auxiliary winding. 5 gnd ground 6 fb feedback . typically, an opto-coupler is connected to th is pin to provide feedback information to the internal pwm comparator. this feedback is used to control the duty cycle in cv regulation. 7 nc no connect 8 hv high voltage . this pin connects to the dc bus for high-voltage startup. hv nc fb gnd cs gate vdd vs f - fairchild logo z: assembly plant code x: year code y: week code tt: die run code t: m=soic p: y= green package m: manufacture flow code ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 4 FAN302HLMY_f117? mwsaver? pwm c ontroller for low standby power battery-charger applications absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v hv hv pin input voltage 500 v v vdd dc supply voltage (1,2) 30 v v vs vs pin input voltage -0.3 7.0 v v cs cs pin input voltage -0.3 7.0 v v fb fb pin input voltage -0.3 7.0 v p d power dissipation (t a =25 c) 660 mw ja thermal resistance (junction-to-air) 150 c/w jc thermal resistance (junction-to-case) 39 c/w t j operating junction temperature -40 +150 c t stg storage temperature range -55 +150 c t l lead temperature, (wave soldering or ir, 10 seconds) +260 c esd electrostatic discharge capability human body model, jedec:jesd22_a114 (except hv pin) (3) 5000 v charged device model, jedec:jesd22_c101 (except hv pin) (3) 1500 notes: 1. all voltage values, except differential vo ltages, are given with respect to gnd pin. 2. stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device. 3. esd ratings including the hv pin: hbm=400v, cdm=750v. ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 5 FAN302HLMY_f117? mwsaver? pwm c ontroller for low standby power battery-charger applications electrical characteristics v dd =15v and t a =25 c unless noted. symbol parameter condition min. typ. max. unit hv section v hv-min minimum startup voltage on hv pin 50 v i hv supply current drawn from hv pin v hv =100v, v dd =0v, controller off 0.8 1.5 5.0 ma i hv-lc leakage current drawn from hv pin v hv =500v, v dd =15v (controller on with auxiliary supply) 0.8 3.0 a v dd section v op continuous operation voltage limited by v dd over-voltage protection (ovp) 25 v v dd-on turn-on threshold voltage v dd rising 15 16 17 v v dd-off turn-off threshold voltage v dd falling 4.7 5.0 5.3 v v dd-lh threshold voltage for latch-off release v dd falling 2.5 v i dd-st startup current v dd =v dd-on ? 0.16v 400 450 a i dd-op operating supply current v dd =18v, f=f osc , c gate =1nf 3.5 4.0 ma i dd-burst burst-mode operating supply current v dd =8v, c gate =1nf 200 350 a v dd-ovp v dd over-voltage protection level 25.0 26.5 28.0 v t d-vddovp v dd over-voltage protection debounce time f=85khz 100 180 s oscillator section f osc frequency center frequency v cs =5v, v s =2.5, v fb =5v 82 85 88 khz hopping range 3 f osc-cm-min minimum frequency for continuous conduction mode (ccm) prevention circuit (4) 13 18 23 khz f osc-ccm minimum frequency in constant current (cc) regulation v cs =5v, v s =0v 23 26 29 khz feedback input section a v internal voltage scale-down ratio of fb pin (5) 1/3.5 1/3.0 1/2.5 v/v z fb fb pin input impedance 38 42 44 k ? v fb-open fb pin pull-up voltage fb pin open 5.3 v v fb-l fb threshold to disable gate drive in burst mode v fb falling,v cs =5v, v s =0v 1.2 1.4 1.6 v v fb-h fb threshold to enable gate drive in burst mode v fb rising,v cs =5v, v s =0v 1.3 1.5 1.7 v over-temperature protection section t otp threshold for over-temperature protection (ovp) +130 +140 +150 c continued on the following page? ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 6 FAN302HLMY_f117? mwsaver? pwm c ontroller for low standby power battery-charger applications electrical characteristics (continued) v dd =15v and t a =25 c unless noted. symbol parameter condition min. typ. max. unit voltage-sense section i tc bias current v cs =5v 8.75 10.00 11.25 a v vs-cm-min v s sampling voltage to switch to the second pulse-by-pulse current limit in power limit mode (6) 0.55 v v vs-cm-max v s sampling voltage to switch back to the normal pulse-by-pulse current limit (6) 0.75 v v sn-cc v s sampling voltage to start frequency decreasing in cc mode v cs =5v, f s1 =f osc -2khz 2.05 2.15 2.25 v v sg-cc vs sampling voltage to end frequency decreasing in cc mode v cs =5v, f s2 =f osc-ccm +2khz 0.45 0.70 0.95 v s g-cc frequency decreasing slope of cc regulation s g-cc = (f s1 -f s2 ) / (v sn-cc - v sg-cc ) 30 38 46 khz/v v vs-offset zcd comparator internal offset voltage (6) 200 mv v vs-ovp output over-voltage protection with v s sampling voltage 2.70 2.80 2.85 v t vs-ovp output over-voltage protection debounce time f osc =85khz 100 180 s current-sense section v vr internal reference voltage for cc regulation 2.475 2.500 2.525 v v ccr variation test voltage on cs pin for cc output (non-inverting input of error amplifier for cc regulation) v cs =0.47v 2.405 2.430 2.455 v v sth normal current limit threshold voltage 0.8 v v sth-va second current limit threshold voltage, power limit mode (v s ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 8 FAN302HLMY_f117? mwsaver? pwm c ontroller for low standby power battery-charger applications typical performance characteristics figure 12. leave zero duty cycle of fb v oltage (v fb-h ) vs. temperature figure 13. v s ove r - v oltage protection (v vs-ovp ) vs. temperature figure 14. reference voltage of cs ( v vr ) vs. temperature figure 15. v ariation v oltage on cs pin for constant- current regulation (v ccr ) vs. temperature figure 16. starting voltage of frequency decreasing of cc regulation (v sn-cc ) vs. temperature figure 17. ending voltage of frequency decreasing of cc regulation (v sg-cc ) vs. temperature 1.20 1.30 1.40 1.50 1.60 1.70 1.80 -40 -30 -15 0 25 50 75 85 100 125 v fb-h (v) temperature (oc) 2.65 2.70 2.75 2.80 2.85 2.90 2.95 -40 -30 -15 0 25 50 75 85 100 125 v vs-ovp (v) temperature (oc) 2.47 2.48 2.49 2.50 2.51 2.52 2.53 -40 -30 -15 0 25 50 75 85 100 125 v vr (v) temperature (oc) 2.38 2.40 2.42 2.44 2.46 2.48 2.50 -40 -30 -15 0 25 50 75 85 100 125 v ccr (v) temperature (oc) 2.08 2.10 2.12 2.14 2.16 2.18 2.20 -40 -30 -15 0 25 50 75 85 100 125 v sn-cc (v) temperature (oc) 0.665 0.668 0.671 0.674 0.677 0.680 0.683 -40 -30 -15 0 25 50 75 85 100 125 v sg-cc (v) temperature (oc) ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 9 FAN302HLMY_f117? mwsaver? pwm c ontroller for low standby power battery-charger applications typical performance characteristics figure 18. threshold voltage for current limit ( v sth ) vs. temperature figure 19. threshold voltage for current limit at power mode (v sth-va ) vs. temperature figure 20. minimum on time (t min ) vs. temperature figure 21.leading-edge blanking time (t leb ) vs. temperature figure 22. maximum duty cycle (dcy max ) vs. temperature figure 23. gate output clamp voltage ( v gate-clamp ) vs. temperature 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 -40 -30 -15 0 25 50 75 85 100 125 v sth (v) temperature (oc) 0.15 0.20 0.25 0.30 0.35 0.40 0.45 -40 -30 -15 0 25 50 75 85 100 125 v sth-va (v) temperature (oc) 530 540 550 560 570 580 590 -40 -30 -15 0 25 50 75 85 100 125 t min (ns) temperature (oc) 66.4 66.6 66.8 67.0 67.2 67.4 67.6 -40 -30 -15 0 25 50 75 85 100 125 dcy max (%) temperature (oc) 13.5 14.0 14.5 15.0 15.5 16.0 16.5 -40 -30 -15 0 25 50 75 85 100 125 v gate-clamp (v) temperature (oc) ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 10 FAN302HLMY_f117 ? mwsaver? pwm c ontroller for low standby power battery-charger applications operational description basic control principle figure 24 shows the internal pwm control circuit. the constant voltage (cv) regul ation is implemented in the same way as the conventional isolated power supply, where the output voltage is sensed using a voltage divider and compared with the internal 2.5v reference of a shunt regulator (ka431) to generate a compensation signal. the compensation signal is transferred to the primary side using an opto-coupler and scaled down through attenuator av, generating the v ea.v signal. then the error signal v ea.v is applied to the pwm comparator (pwm.v) to determine the duty cycle. meanwhile, the cc regulation is implemented internally without directly sensing t he output current. the output current estimator reconstructs output current information (v ccr ) using the transformer primary-side current and diode current discharge time. then v ccr is compared with a reference voltage (2.5 v) by an internal error amplifier, generating the v ea.i signal to determine the duty cycle. the two error signals, v ea.i and v ea.v , are compared with an internal sawtooth waveform (v saw ) by pwm comparators pwm.i and pwm. v to determine the duty cycle. as shown in figur e 25, the outputs of two comparators (pwm.i and pwm.v) are combined with an or gate and used as a reset signal of flip-flop to determine the mosfet turn-off instant. the lower signal, v ea.v or v ea.i , determines the duty cycle, as shown in figure 25. during cv regulation, v ea.v determines the duty cycle while v ea.i is saturated to high. during cc regulation, v ea.i determines the duty cycle while v ea.v is saturated to high. figure 24. internal pwm control circuit cv regulation cc regulation v saw v ea.i v ea.i v ea.v v ea.v pwm.v pwm.i osc clk gate figure 25. pwm operation for cc and cv output current estimation figure 26 shows the key waveform of a flyback converter operating in discontinuous conduction mode (dcm), where the secondary-side diode current reaches zero before the next switching cycle begins. since the output current estimator is designed for dcm operation, the power stage should be designed such that dcm is guaranteed for the entire oper ating range. the output current is obtained by averaging the triangular output diode current area over a switching cycle: s dis s p pk avg d o t t n n i i i 2 ? = > =< (1) where i pk is the peak value of the primary-side current; n p and n s are the number of turns of transformer primary-side and secondary-side, respectively; t dis is the diode current discharge time; and t s is the switching period. with a given current sensing resistor, the output current can be programmed as: s p sense o n n r k i ? = 25 . 1 (2) where k is the design parameter of ic, which is 10.5. the peak value of primary-side current is obtained by an internal peak detection circuit, while diode current discharge time is obtained by detecting the diode current zero-crossing instant. since the diode current cannot be sensed directly wi th primary-side control, zero crossing detection (zcd) is accomplished indirectly by monitoring the auxiliary winding voltage. when the diode current reaches zero, the transformer winding voltage begins to drop by the resonance between the mosfet output capacitance and the transformer magnetizing inductance. to detect the starting instant of t he resonance, the v s is sampled at 85% of diode current discharge time of the previous switching cycle, then com pared with the instantaneous v s voltage. when instantaneous v s drops below the sampled voltage by more than 200mv, zcd of diode current is obtained, as shown in figure 27. ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 11 FAN302HLMY_f117 ? mwsaver? pwm c ontroller for low standby power battery-charger applications p pk s n i n ? p k i d avg o ii <>= figure 26. key waveforms of dcm flyback converter figure 27. detailed waveform for zcd frequency reduction in cc mode an important design cons ideration is that the transformer guarantee dcm operation across the whole range since the output current is properly estimated only in dcm operation. as can be seen in figure 28, the discharge time (t dis ) of the diode current increases as the output voltage decr eases in cc mode. the converter tends to go into ccm as output voltage drops in cc mode when operating at the fixed switching frequency. to prevent this ccm operation while maintaining good output current estimation in dcm, FAN302HLMY_f117 decreases switching frequency as output voltage drops, as shown in figure 28 and figure 29. FAN302HLMY_f117 indirectly monitors the output voltage by the sample-and-hold voltage (v sh ) of v s , which is taken at 85% of diode current discharge time of the previous switching cycle, as shown in figure 27. figure 30 shows how the frequency reduces as the sample-and-hold voltage of vs decreases. figure 28. t dis variation in cc mode figure 29. frequency reduction with v sh cc g s v f ? = figure 30. frequency reduction curve in cc regulation ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 12 FAN302HLMY_f117 ? mwsaver? pwm c ontroller for low standby power battery-charger applications ccm prevention function even if the power supply is designed to operate in dcm, it can go into ccm when there is not enough design margin to cover all the circuit parameter variations and operating conditions. FAN302HLMY_f117 has a ccm- prevention function that delays the next cycle turn-on of mosfet until zcd on the vs pin is obtained, as shown in figure 31. to guarantee stable dcm operation, FAN302HLMY_f117 prohibits the turn-on of the next switching cycle for 10% of its switching period after zcd is obtained. in figure 31, t he first switching cycle has zcd before 90% of its origi nal switching period and, therefore, the turn-on inst ant of the next cycle is determined without being affected by the zcd instant. the second switching cycle does not have zcd by the end of the original switching period; thus, the turn-on of the third switching cycle occurs after zcd is obtained, with a delay of 10% of its original switching period. the minimum switching frequency that ccm prevention function allows is 18khz (f osc-cm-min ). if the zcd is not given until the end of maximum switching period of 55.6s (1/18khz), the conv erter can go into ccm operation, losing output regulation. figure 31. ccm prevention function power limit mode when the sampled voltage of vs (v sh ) drops below v s- cm-min (0.55v), FAN302HLMY_f117 enters constant power limit mode, where the primary-side current-limit voltage (v cs ) changes from v sth (0.8v) to v sth-va (0.3v) to avoid v s sampling and zcd, as shown in figure 32. once v s sampling voltage is higher than v s-cm-max (0.75v), the v cs returns to v sth . this mode prevents the power supply from going into ccm and losing output regulation when the output voltage is too low. this effectively protects the po wer supply when there is a fault condition in the load, such as output short or overload. this mode also implements soft-start by limiting the transformer current until v s sampling voltage reaches v s-cm-max (0.75v). figure 32. power limit mode operation high-voltage startup figure 33 shows the high-voltag e (hv) startup circuit. internally, jfet is used to implement the high-voltage current source, whose characteristics are shown in figure 34. technically, the hv pin can be directly connected to the dc link (v dl ). to improve reliability and surge immunity; it is typical to use about a 100k ? resistor between the hv pi n and the dc link. the actual hv current with given dc link voltage and startup resistor is determined by the intersection of v-i characteristics line and load line, as shown in figure 34. during startup, the internal startup circuit is enabled and the dc link supplies the current, i hv , to charge the hold- up capacitor, c vdd , through r start . when the v dd voltage reaches v dd-on , the internal hv startup circuit is disabled and the ic starts pwm switching. once the hv startup circuit is disabled, the energy stored in c vdd should supply the ic operating current until the transformer auxiliary winding voltage reaches the nominal value. therefore, c vdd should be designed to prevent v dd from dropping to v dd-off before the auxiliary winding builds up enough voltage to supply v dd . figure 33. hv startup circuit ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 13 FAN302HLMY_f117 ? mwsaver? pwm c ontroller for low standby power battery-charger applications dl hv hv hv vv i r ? = d l h v v r dl v figure 34.v-i characteristics of hv pin frequency hopping emi reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth of the emi test equipment. the frequency-hopping circuit changes the switching frequency progressively between 82khz and 88khz with a period of t p , as shown in figure 35. figure 35. frequency hopping burst-mode operation the power supply enters burst mode at no-load or extremely light-load conditions. as shown in figure 36, when v fb drops below v fbl ; the pwm output shuts off and the output voltage drops at a rate dependent on load current. this causes the feedback voltage to rise. once v fb exceeds v fbh , the internal circuit starts to provide switching pulse. the feedback voltage then falls and the process repeats. burst mode operation alternately enables and dis ables switching of the mosfet, reducing the switching losses in standby mode. once FAN302HLMY_f117 enters burst mode, the operating current is reduced from 3.5ma to 200 a to minimize power consumption. figure 36. burst-mode operation slope compensation the sensed voltage across the current-sense resistor is used for current-mode control and pulse-by-pulse current limiting. a synchronized ramp signal with positive slope is added to the current sense information at each switching cycle, im proving noise immunity of current-mode control. protections the self-protection functions include v dd over-voltage protection (ovp), internal over-temperature protection (otp), v s over-voltage protection (ovp), and brownout protection. v dd ovp and brownout protection are implemented as auto-restart mode, while the v s ovp and internal otp are implemented as latch mode. when an auto-restart mode protection is triggered, switching is terminated and the mosfet remains off, causing v dd to drop. when v dd drops to the v dd turn-off voltage of 5v; the protection is reset, the internal startup circuit is enabled, and the supply current drawn from the hv pin charges the hold-up capacitor. when v dd reaches the turn-on voltag e of 16v, normal operation resumes. in this manner , auto-restart alternately enables and disables mosfet switching until the abnormal condition is eliminated, as shown in figure 37. when a latch mode protection is triggered, pwm switching is terminated and the mosfet remains off, causing v dd to drop. when v dd drops to the v dd turn-off voltage of 5v, the internal startup circuit is enabled without resetting the protection and the supply current drawn from hv pin charges the hold-up capacitor. since the protection is not reset, the ic does not resume pwm switching even when v dd reaches the turn-on voltage of 16v, disabling hv startup circuit. then v dd drops down to 5v. in this manner, the latch mode protection alternately charges and discharges v dd until there is no more energy in the dc link capacitor. the protection is reset when v dd drops to 2.5v, which is allowed only after the power supply is unplugged from the ac line, as shown in figure 38. ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 14 FAN302HLMY_f117 ? mwsaver? pwm c ontroller for low standby power battery-charger applications figure 37. auto-restart mode operation figure 38. latch-mode operation over-temperature protection (otp) the temperature-sensing circuit shuts down pwm output if the junction temperature exceeds 140c (t otp ). v dd over-voltage protection v dd over-voltage protection prevents ic damage from over-voltage exceeding the ic voltage rating. when the v dd voltage exceeds 26.5v due to an abnormal condition, the protection is triggered. this protection is typically caused by open circuit in the secondary-side feedback network. v s over-voltage protection (ovp) v s over-voltage protection prevents damage due to output over-voltage conditions. figure 39 shows the v s ovp protection method. when abnormal system conditions occur that cause v s to exceed 2.8v, after a period of debounce time; pwm pulses are disabled and FAN302HLMY_f117 enters latch mode until v dd drops under v dd-lh . by that time, pwm pulses revive. v s over- voltage conditions are usually caused by open circuit of the secondary-side feedback network or abnormal behavior by the vs pin divider resistor. figure 39. v s ovp protection leading-edge blanking (leb) each time the power mosfet is switched on, a turn-on spike occurs at the sense re sistor. to avoid premature termination of the switching pu lse, a 150ns leading-edge blanking time is built in. conventional rc filtering can therefore be omitted. during this blanking period, the current-limit comparator is disabled and it cannot switch off the gate driver. noise immunity noise from the current sens e or the control signal can cause significant pulse-width jitter. while slope compensation helps alleviate these problems, further precautions should still be ta ken. good placement and layout practices should be followed. avoid long pcb traces and component lead s. locate bypass filter components near the pwm ic. ? 2012 fairchild semiconductor corpor ation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 15 FAN302HLMY_f117 ? mwsaver? pwm c ontroller for low standby power battery-charger applications typical application circuit (flyback charger) application fairchild device input voltage range output cell phone charger FAN302HLMY_f117 90~265v ac 5v/1.2a (6w) features ? high efficiency (>71% avg.), meets ener gy star v2.0 standard (avg. 68.17%) ? ultra-low standby power co nsumption, <10mw at 230v ac (pin=6.3mw for 115v ac and pin=7.3mw for 230v ac ) ? output regulation: cv= 5%, cc= 15% figure 40. measured efficiency and output regulation n p n s r 1 0 c 4 + v d l - a c l i n e d 7 c 8 v o c 1 r 1 2 c 6 i o r 9 c 9 r 2 0 t l 4 3 1 c 7 r 1 8 r 1 7 r 1 1 0 ? c 2 l 1 c 3 c s v d d v s h v f b g a t e g n d f a n 3 0 2 h l m y _ f 1 1 7 1 2 3 4 5 6 8 n c 7 r 5 r 4 n a r 7 r 8 d 5 d 6 d 1 ~ d 4 f f m 1 0 7 m * 4 6 . 8 f 6 . 8 f 1 m h 2 7 0 k ? 4 7 0 p f f f m 1 0 7 m 1 0 n f 1 k ? 6 4 . 9 k ? 6 3 . 4 k ? l 3 1 . 8 h 1 0 0 ? 1 . 3 ? 9 1 k ? 4 0 . 2 k ? i n 4 9 3 5 3 3 f 4 7 ? 3 a / 4 0 v 1 0 ? 1 n f 3 3 0 f 3 3 0 f c 1 1 4 7 0 p f q 1 4 a / 6 5 0 v d 9 r 2 1 0 ? 1 n 4 1 4 8 e i 1 2 . 5 9 3 t / 7 t / 1 1 t c 5 2 0 p f c 1 0 1 n f r 3 0 ? u 1 r 1 1 5 . 6 k ? f o d 8 1 7 s r 6 0 ? figure 41.schematic of typical application circuit ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 16 FAN302HLMY_f117 ? mwsaver? pwm controller for low standby power battery-charger applications typical application circuit (continued) transformer specification ? core: ei12.5 ? bobbin: ei12.5 2 1 bobbin 4 5 auxiliary winding primary winding fly+ fly? secondary winding figure 42.transformer notes: 7. w1 consists of four layers with different number of tu rns. the number of turns of eac h layer is specified in table 1. add one insulation tape between the second and third layers. 8. w2 consists of two layers with triple-insulated wi re. the leads of positive and negative fly lines are 3.5cm and 2.5cm, respectively. 9. w3 is space winding in one layer. table 1. transformer winding specifications no. terminal wire turns insulation start pin end pin turns w1 4 5 2uew 0.1*1 26 0 25 1 24 0 18 2 w2 fly+ fly- tex-e 0.45*1 7 2 w3 1 2 2uew 0.18*1 11 2 core rounding tape 3 core 0 w4 2 2uew 0.18*1 5 2 note: 10. w4 is the outermost and space winding. pin specifications remark primary-side inductance 4 5 700 h 7% 100khz, 1v primary-side leakage inductance 4 5 130 h 7% short one of the secondary-side windings ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 17 FAN302HLMY_f117 ? mwsaver? pwm controller for low standby power battery-charger applications physical dimensions figure 43. 8-lead, small outline package (soic), jedec ms-012, .150-inch, narrow body package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FAN302HLMY_f117 ? rev. 1.0.1 18 FAN302HLMY_f117 ? mwsaver? pwm controller for low standby power battery-charger applications |
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